000			00815nam a2200265 4500
008			180517t2003 xxu||||| |||| 00| 0 eng d
020			_a9172836318
041			_aeng
080			_a621.3.049.77 _bP3
942			_cBK
100			_aPamunuwa, Dinesh
245			_aModelling and analysis of interconnects for deep submicron systems- on-chip
260			_aStockholm _c2003 _bRoyal Institute of Technology
300			_axiv, 163p. : ill., charts, tables
650			_aDELAY AND NOISE MODELLING IN VLSI CIRCUITS
650			_aCROSS-TALK
650			_aINTERCONNECT MODELLING
650			_aTiming analysis
650			_aTransfer function
650			_aOn-chip bus
650			_aBandwidth maximization
650			_aThroughput maximization
650			_aRepeater insertion
650			_aWire optimization
999			_c175070 _d175070