TY  - BOOK
AU  - Pamunuwa, Dinesh
TI  - Modelling and analysis of interconnects for deep submicron systems- on-chip
SN  - 9172836318
PY  - 2003///
CY  - Stockholm
PB  - Royal Institute of Technology
KW  - DELAY AND NOISE MODELLING IN VLSI CIRCUITS
KW  - CROSS-TALK
KW  - INTERCONNECT MODELLING
KW  - Timing analysis
KW  - Transfer function
KW  - On-chip bus
KW  - Bandwidth maximization
KW  - Throughput maximization
KW  - Repeater insertion
KW  - Wire optimization
ER  -